In the fabrication of semiconductor memory devices, it is common for an array of memory cells to include one or more defects which prevent the proper performance of the memory circuit. If a type of defect occurs systematically it can often be causally analyzed and designed out. Other defects which are generally not systematic include short circuits between adjacent columns and open circuits within individual columns of memory cells. For analysis purposes, the distribution of such defects in a memory device, as well as the distribution of the number of defects among a given production lot, may be considered random so that the yield of good devices in a lot can be modelled according to a Poisson distribution function. Typically, over the period of time that a particular device or family of devices is being produced in a given manufacturing facility, the product yield can be improved by removing causes, e.g., particulate matter, of the above-mentioned random defects.
In many fabrication processes, the causes of random defects cannot be completely eliminated and it is desirable to further improve the yield of memory devices with redundant circuitry. During testing of a chip, defective memory cells can be identified and replaced. Such redundancy techniques are especially suited for semiconductor memories because large numbers of repeating elements are arranged in columns and rows. This array format lends itself to replacement of a defective column or row with any of multiple identical redundant columns or rows.
A redundant circuit scheme may be implemented with a plurality of universal decode circuits connected to the redundant columns. To activate the redundant circuitry, appropriate fuses ar included for programming individual decoder circuits to be responsive to the addresses of defective memory cells. For example, in dynamic random access memory devices (DRAM's), address integrity can be maintained by simply programming redundant column circuits to respond to defective column addresses. Thus, the address of each defective column is assigned to a redundant column circuit. In video and frame memory circuits, the replacement procedure may require greater complexity in order to maintain the sequential nature of memory output. See U.S. Pat. No. 4,598,388 assigned to the assignee of the present invention.
Semiconductor memories of all types are being made with progressively higher bit densities and smaller cell sizes as the density of integrated memory circuits increases. In 1972, 4K bit DRAMs were being designed, while in 1982, one megabit devices were planned. Sixteen megabit device densities will become mass produced during the 1990's. As memory capacity continues to progress, there must be further improvement in associated performance parameters such as memory access time. As a result memory architectures, which have already become relatively complex, are likely to become even more elaborate as device densities increase.
In order to improve performance, it is now commonplace to partition higher density memory arrays into logical data blocks wherein all cells associated with a particular block have common I/O paths. With this arrangement, data blocks in an array can be individually accessed. Accordingly, each data word, e.g., possibly 16 or 32 bits wide in a 64 Megabit device, could be stored entirely within one of the blocks so that the entire word can be retrieved from the memory at a given time. Thus, there is no loss in availability of data. Advantageously, the blocks in a partitioned array have shorter signal paths, smaller propagation delays and hence faster access times. Further, since only one of many blocks is accessed at a time, the overall device power consumption is also reduced.
Such partitioning requires that at least some of the support circuitry, which functions to select desired memory locations as well as to sense and maintain data states, be repeated for each data block. When the concept of internally partitioning a memory array into smaller logical data blocks was introduced, the memory densities were lower than now achievable and repetition of support circuitry for each data block was an acceptable cost in view of the above-noted performance benefits. That is, the resulting increase in chip size over that required for a slower, more power consuming array design was not critical.
Now, with the development of even denser memory devices, the requisite reduction in feature sizes renders these circuits susceptible to defects caused by particulate matter which previously caused no problems in the fabrication process. Thus, with further improvements in circuit density, there will be a greater challenge to eliminate random-type defects. Accordingly, greater reliance may be placed on redundant circuit repair schemes.
In theory, by providing a sufficient number of redundant circuits on a device, all column defects of the type described above would be repairable in order to maximize the yield of a production lot. Practically, however, cost effectiveness usually dictates that space constraints will limit the quantity of redundant circuits to be placed on each integrated circuit. It is undesirable to increase repair circuitry in proportion to memory density.